1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with a level shifter circuit and, more particularly, to a semiconductor integrated circuit used to decrease a through current in an inverter circuit which uses an output signal of the level shifter circuit as an input signal.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional interface circuit between a low-voltage system (referred to as a -E1 system hereinafter) and a high-voltage system (referred to as a -E2 system hereinafter). The interface shown in FIG. 1 is connected between a -E1 system logic circuit 1a and a -E2 system logic circuit 5, and comprises a -E1 system inverter circuit 1, a -E2 system flip-flop circuit 2, and a -E2 system inverter circuit 3. The -E1 system inverter circuit 1 and the -E2 system flip-flop circuit 2 constitute a voltage conversion circuit (level shifter circuit). The -E1 system logic circuit 1a outputs a digital input signal IN alternating between the ground voltage GND and a first voltage (first power supply voltage) -El (low voltage). The -E1 system inverter circuit 1 receives the input signal IN and outputs a signal IN (the inversion signal of signal IN). The -E2 system flip-flop circuit 2 uses the input signal IN and the output signal e,ovs/IN/ of the -E1 system inverter circuit 1 as input signals, and is connected between the ground voltage GND and a second voltage (second power supply voltage) -E2 (high voltage). The -E2 system inverter circuit 3 waveform-shapes the output signal of the level shifter circuit or the output signal of the -E2 system flip-flop circuit 2, and supplies the shaped signal as the input signal to the -E2 system logic circuit 5.
FIG. 2 shows a concrete arrangement of the interface circuit of FIG. 1, which is composed of complementary MOSFETs formed on an N-type semiconductor substrate. The -E1 system logic circuit 1a and -E2 system logic circuit 5 of FIG. 1 are not shown in FIG. 2. The -E1 system inverter circuit 1 is composed of a P-channel MOSFET P11 and an N-channel MOSFET N11. The gate of each of the P-channel MOSFET P11 and N-channel MOSFET N11 is supplied with the input signal IN1. One end of the current path of the P-channel MOSFET P11 is grounded and the other end is connected to one end of the current path of the N-channel MOSFET N11. The other end of the N-channel MOSFET N11 is supplied with the first voltage -El. The output terminal of the -E1 system inverter circuit 1 supplies the inverted signal IN1. The -E2 system flip-flop circuit 2 is composed of P-channel MOSFETs P12 and P13 and N-channel MOSFETs N12 and N13, and uses the input signal IN1 and the inverted signal IN1 as input signals and outputs a signal alternating between the ground voltage GND and the second voltage -E2. The -E2 system flip-flop circuit 2 outputs a signal of opposite phase to the input signal IN1. Specifically, the flip-flop circuit 2 outputs a signal at the level of the second voltage -E2 when the input signal IN1 is at the level of the ground voltage GND, and outputs a signal at the ground voltage GND when the input signal IN1 is at the first voltage -El. The gate electrodes of the P-channel MOSFETs P12 and P13 are supplied with the input signal IN1 and the inverted signal IN1, respectively. One ends of the current paths of the P-channel MOSFETs 12 and 13 are grounded, respectively. The other end of the current path of the P-channel MOSFET P12 is connected to one end of the current path of the N-channel MOSFET N12. This connection point is connected to the gate electrode of the N-channel MOSFET N13 and the input terminal of the -E2 system inverter circuit 3d. The other end of the current path of the P-channel MOSFET P13 is connected to one end of the current path of the N-channel MOSFET N13. This connection point is connected to the gate electrode of the N-channel MOSFET N12. The other ends of the current paths of the N-channel MOSFETs N12 and N13 are supplied with the second voltage -E2. To stabilize the circuit operation, the amplification factors of the P-channel MOSFETs P12 and P13 and the N-channel MOSFETs N12 and N13 constituting the -E2 system flip-flop circuit 2 are set as follows: gm.sub.p12 &gt;gm.sub.N12, gm.sub.p13 &gt;gm.sub.N13, gm.sub.p12 =gm.sub.p13, and gm.sub.N12 =gm.sub.N13. Where gm.sub.p12 is the amplification factor of the P-channel MOSFET P12, and gm.sub.N12, gm.sub.p13, and gm.sub.N13 indicate the amplification factors of the corresponding MOSFETs. The -E2 system inverter circuit 3d is composed of a P-channel MOSFET P14 and an N-channel MOSFET N14. One end of the current path of the P-channel MOSFET P14 is grounded and the other end is connected to one end of the current path of the N-channel MOSFET N14, the other end of which is supplied with the second voltage -E2. The connection of the gate electrodes of the P-channel MOSFET P14 and the N-channel MOSFET N14 is the input terminal of the -E2 system inverter circuit 3d. The connection of the other end of the current path of the P-channel MOSFET P14 and one end of the current path of the N-channel MOSFET N14 is the output terminal of the -E 2 system inverter circuit 3d. At the output terminal, an output signal OUT1 is supplied.
FIG. 3 is a timing chart for the operation of the interface circuit of FIG. 2. The operation of the interface circuit will be explained when the input signal IN1 changes from the ground voltage GND (high level) to the first voltage -El (low level), as shown in FIG. 3(a). As shown in FIG. 3(a), when the input signal IN1 is at the ground voltage GND, the inverted signal IN1 is at the first voltage -El as shown in FIG. 3(b). A point A is at the second voltage -E2, a point B is at the ground voltage GND, and the output signal OUT1 is at the ground voltage GND, as shown in FIGS. 3(c) through (e). In this state, as shown in FIG. 3(c), the potential at the point A equals the second voltage -E2, the N-channel MOSFET N13 is off and the point B remains at the ground voltage GND. In this state, since the N-channel MOSFET N14 is off, a through current does not flow in the P-channel MOSFET P14 and N-channel MOSFET N14. In this state, when the potential of the input signal IN1 changes to the first voltage -E1 as shown in FIG. 3(a), the potential of the inverted signal IN1 goes to the ground voltage GND, causing the P-channel MOSFET P12 to turn on and the P-channel MOSFET P13 to turn off. Therefore, the potential of the point A corresponds to the resistance division ratio (voltage division ratio) of the P-channel MOSFET P12 and the N-channel MOSFET N12. According to the relationship between the amplification factor gm.sub.p12 of the P-channel MOSFET P12 and the amplification factor gm.sub.N12 of the N-channel MOSFET N12, the potential of the point A changes gradually from the second voltage -E2 to the ground voltage GND, as shown in FIG. 3(c). On the other hand, the change of the potential at the point A places the N-channel MOSFET N13 in an ON state and the potential at the point B changes from the ground voltage GND to the second voltage -E2, as shown in FIG. 3(d). As a result, the N-channel MOSFET N12 goes to the OFF state and the potential at the point A changes from the second voltage -E2 to the ground voltage GND. In this way, because the potential at the point A is determined by the resistance division between of the p-channel MOSFET P12 and N-channel MOSFET N12 and the interaction with the potential of the point B, it changes gradually without a normal CMOS operation which is seen in the -E1 system inverter circuit 1. As describe above, in accordance with the potential at the point A changing from the second voltage -E2 to the ground voltage GND, the P-channel MOSFET P14 turns off and the N-channel MOSFET N14 turns on. This causes the potential of the output signal OUT1 to change from the ground voltage GND to the second voltage -E2.
Then, the operation of the interface circuit will be explained when the input signal IN1 changes from the first voltage -El to the ground voltage GND, as shown in FIG. 3(a). When the input signal IN1 is at the first voltage -E1, the inverted signal IN1 is at the ground voltage GND, the point A is at the ground voltage GND, the point B is at the second voltage -E2, and the output signal OUT1 is at the second voltage -E2. In this state, because the point A is at the ground voltage GND, the P-channel MOSFET P14 turns off, with the result that a through current does not flow in the -E2 system inverter circuit 3. In this case, when the input signal IN1 changes to the ground voltage GND, the inverted signal IN1 goes to the first voltage -El. This causes the P-channel MOSFET P12 to turn off and the P-channel MOSFET P13 to turn on. As a result, the potential at the point B corresponds to the resistance division ratio of the P-channel MOSFET P13 to the N-channel MOSFET N13. According to the relationship of gm.sub.p13 &gt;gm.sub.N13, the potential at the point B gradually changes from the second voltage -E2 to the ground voltage GND. On the other hand, the change of the potential at the point B causes the N-channel MOSFET N12 to turn on. The potential at the point A thus changes to the second voltage -E2. The change of the potential at the point A causes the N-channel MOSFET N13 to go to the OFF state. Therefore, the potential at the point B finally equals the ground voltage GND and the potential at the point A goes to the second voltage -E2. In this way, since the potential at the point A is determined by the resistance division between the P-channel MOSFET P13 and N-channel MOSFET N13 and the interaction with the potential of the point B, it changes gradually without a normal CMOS operation, as seen in the -1 system inverter circuit 1. The second voltage -E2 at the point A is supplied to the gate electrodes of the P-channel MOSFET P14 and the N-channel MOSFET N14. This causes the P-channel MOSFET P14 to turn on and the N-channel MOSFET N14 to turn off, placing the potential of the output signal OUT1 at the ground voltage GND.
FIG. 4 shows a second conventional interface circuit. The interface circuit of FIG. 4 differs from that of FIG. 2 in the following points. In FIG. 2, the input terminal of the -E2 system inverted circuit 3d is connected to the gate electrode of the N-channel MOSFET N13 and the connection of the other end of the current path of the P-channel MOSFET P12 and one end of the current path of the N-channel MOSFET N12. In contrast, the input terminal of the -E2 system inverted circuit 3d of FIG. 4 is connected to the gate electrode of the N-channel MOSFET N12 and the connection of the other end of the current path of the P-channel MOSFET P13 and one end of the current path of the N-channel MOSFET N13. The remaining parts of the interface circuit of FIG. 4 is the same as that of FIG. 2, so that the same parts as those in FIG. 2 are indicated by the same reference characters and their explanation will be omitted. Further, the interface circuit of FIG. 4 differs from that of FIG. 2 in that the former supplies the output signal of an opposite phase to the input signal IN1. Specifically, in the interface circuit of FIG. 4, the output signal of the -E2 system inverter circuit 3d equals the second voltage -E2 when the input signal IN1 is at the ground voltage GND, and the same output signal goes to the ground voltage GND when the input signal IN1 is at the first voltage -El. Therefore, the inverted signal IN1 and the potentials at points A and B change as shown in FIGS. 3(b) through (d).
However, when the input signal IN1 changes from the ground voltage GND to the first voltage -E1 as in the first conventional example, the potential at the point B changes gradually, and the -E2 system flip-flop circuit does not perform a normal CMOS operation and changes gradually. This causes a period of time when the P-channel MOSFET P14 and N-channel MOSFET N14 turn on simultaneously, permitting a through current to flow through the -E2 system inverter circuit 3 between the ground voltage GND and the second voltage -E2. Further, when the input signal IN1 changes from the first voltage -E1 to the ground voltage GND, the potential at the point A does not perform a normal CMOS operation and changes gradually. This causes a period of time when the P-channel MOSFET P14 and N-channel MOSFET N14 of the -E2 system inverter circuit turn on simultaneously, permitting the through current to flow between the ground voltage GND and the second voltage -E2.